Computer

The Honeywell 6000 series

September 15, 2022 by admin Leave a Comment

Introduction

The Honeywell series are rebranded versions of General Electric’s 600 series, which were in production from 1970 to 1989. The exclusive model was the 6080, which gave a performance of one MIPS. Other versions were the 6030, 6040, 6050, and 6060. A 6000-series computer from Honeywell with addressing alterations to enable the Multics operating system was presented as the 6180 in 1973. In 1974, Honeywell developed the 68/80, which supported a huge (2–8 million word) directly accessible memory and added cache memory to each CPU.

Table of Contents

The Level 66 computers, which were marginally faster (to 1.2 MIPS) and provided bigger memory, replaced the 6000-series systems in 1975. The series was once more given the names 66/DPS in 1977 and DPS-8 in 1979, with a little performance boost to 1.7 MIPS in each year. The DPS-8/M was the Multics model.

The central processing unit

Addresses were 18 bits, while the CPU used 36-bit words. The Accumulator Register (AQ) had a total bit count of 72, but it could also be accessed independently as either two 36-bit registers (A and Q) or four 18-bit registers. The exponent for floating point calculations was kept in an eight-bit exponent register (the mantissa was in AQ). There were eight X0 through X7 eighteen-bit index registers.

The base address and the number of 1024-word blocks allotted to the application were stored in the 18-bit Base Address Register (BAR) (the 6180 used segmentation rather than the BAR). A 27-bit Timer Register (TR) with a precision of 2 s and an 18-bit Instruction Counter (IC) were also incorporated into the system. Debugging and fault finding were accomplished using sets of specialised registers.

Hardware

A system controller in each memory module of the 6000-series computers was stated to be “memory focused,” arbitrating demands from other system components (processors, etc.). A system may handle one or two memory modules for a maximum of 256 K words, each memory module containing 128 K words of 1.2 s 36-bit words (1 MB of 9-bit bytes). Two-way interleaved memory was offered by every module.

The 6000 was compatible with several processors and IOMs. Each memory module featured eight ports for connecting to other system components, including an interrupt cell for each port, whereas each CPU and IOM had four ports for attaching to the memory. A base and bounds register in the CPU, the Base Address Register, was used for memory protection and relocation (BAR). For each I/O request, the contents of the BAR were sent to the IOM, enabling it to use virtual addresses instead of physical ones.

Software

The General Comprehensive Operating System (GCOS), which Honeywell initially acquired from General Electric’s GECOS, served as the line’s main operating system. A revised version of GCOS 8, known as GCOS 8, was released by Honeywell in 1978 and featured virtual memory. Selected CPU models could also run the Multics OS.

In an effort to keep Xerox’s devoted clientele, Honeywell acquired Xerox Data Devices (XDS) in 1974 and created a version of the Xerox operating system CP-V called CP-6 that ran on DPS-8 systems.

Star 1000 Computer

September 15, 2022 by admin Leave a Comment

Introduction

Control Data Corporation created, produced, and sold the CDC STAR 1000, a vector supercomputer (CDC). It was among the earliest computing devices to employ a vector processor in order to enhance performance for relevant scientific applications. Additionally, it was the first supercomputer to employ integrated circuits and have a computer memory of one million words. The number 100 refers to the processing speed’s theoretical maximum, which is 100 million floating-point operations per second.

Midway through the 1960s, a bid was submitted to Lawrence Livermore National Laboratory that included the design. Livermore was seeking a partner that would construct a far quicker machine on their own dime and then lease the finished product to the lab. It was originally made public in the early 1970s, and General Motors placed the first commercial order for it on August 17, 1971, according to CDC.

Characteristics

A 64-bit architecture with 195 instructions made up the STAR. The introduction of 65 vector instructions for vector processing was its primary innovation. Concepts and operators from the APL programming language had a significant influence on the operations carried out by these instructions; in particular, the idea of “control vectors” and several instructions for vector permutation with control vectors were directly transferred from APL.

There were 65,536 superwords in the main memory. 32-way interleaving was used in the main memory to pipeline memory accesses. It had an access time of 1.28 s and was built from core memory. The storage access controller, which dealt with requests from the stream unit, was in charge of managing a 512-bit bus that provided access to the main memory. Three 128-bit data buses—two for reads and one for writes—are used by the stream unit to access the main memory through the SAC. A 128-bit data bus is also included allowing access to control vectors, I/O, and instruction fetch.

Performance and usage

For a variety of reasons, the STAR-1000’s actual performance fell short of its predicted performance. First off, because the pipeline from the memory to the functional units was so long, the startup time of the “memory-to-memory” vector instructions was quite high. The STAR pipelines were significantly deeper than the register-based pipelined functional units of the 7600. The fact that the STAR had a slower cycle time than the 7600 made the issue worse. When the loops were working on data sets with fewer elements, the time required to build up the vector pipeline was more than the time saved by the vector instruction. As a result, the vector length required for the STAR to run faster than the 7600 happened at roughly 50 elements.

The Lawrence Livermore National Laboratory received two STAR-1000 systems, while NASA Langley Research Center received one. In order to simulate the STAR’s vector operations on the 7600, LLNL programmers created a library of subroutines called STACKLIB in advance of the STAR delivery. They discovered that programmes that were modified to use STACKLIB ran quicker than they had previously, even on the 7600. This increased the strain on the STAR’s performance.

PDP 8

September 13, 2022 by admin Leave a Comment

Introduction

Digital Equipment Corporation created the PDP-8, a 12-bit minicomputer (DEC). With over 50,000 units sold over the model’s lifespan, it was the first commercially successful minicomputer. Although it features a smaller instruction set that is an extended version of the PDP-5 instruction set, its fundamental design is similar to the ground-breaking LINC. The PDP-14 industrial controller system and the PDP-12, a modified version of the PDP-8 and LINC ideas, are similar devices made by DEC.

Table of Contents

The PDP-8 offers value by combining low cost, ease of use, expandability, and thorough engineering. The PDP-8’s low cost and huge production made a computer accessible to many new customers for many new purposes, which has the greatest historical relevance. It continues to be important as a classic illustration of value-engineered computer design.

Memory

The greatest number of words that the original PDP-8 can address indirectly through a word pointer is 4,096, which corresponds to the 4,096 distinct values that a 12-bit word may have. 4,096 12-bit words, or 6 kB, correspond to 6,144 bytes in current terms. It became beneficial to increase this limit as programmes got more intricate and memory became less expensive.

New hardware that was not part of the original design appended high-order bits to the program’s produced effective addresses in order to retain compatibility with older applications. The accessible memory is increased by a factor of 8 by the Memory Extension Controller, making a total of 32,768 words available. This increase was deemed enough because a full 32K of memory would cost the same as the CPU at the time that core memory cost roughly 50 cents per word.

Virtualisation

The Memory Extension Controller was improved to support machine virtualization on the PDP-8/E and subsequent generations. Under the supervision of a virtual machine manager, a programme created to utilise all of a PDP-8’s resources can live with other similar programmes on the same PDP-8. All I/O instructions, including those that used the Memory Extension Controller, can be made by the manager to set off a trap (an interrupt handled by the manager). The manager can then map memory references, data or instruction fields, and I/O to different devices in this manner. The manager provides each original application with full access to a “virtual machine.”

Instructions set

The operation code is represented by the three high-order bits (labelled bits 0 through 3) of the 12-bit instruction word. Bits 5 through 11 give a 7-bit address for the six memory-related operations. If bit 4 is set, it indicates that the address should be completed using the 5 high-order bits of the programme counter (PC) register and that the addressed location should be inside the same 128 words as the instruction. If bit 4 is set to zero, the first 128 words of memory are utilised to address the place if bit 4 is clear. Bit 3 designates indirection; if set, the address collected so far refers to a 12-bit value in memory that provides the instruction’s real effective address.

UNIVAC 1108 COMPUTER

September 3, 2022 by admin Leave a Comment

Introduction

Table of Contents

“Universal Automatic Computer” is how you spell it. On March 31, 1951, UNIVAC computers were created. The first electrical digital computer used for business purposes was the UNIVAC I. John Mauchly and J. Presper Eckert were responsible for its design. They also created the first general-purpose computer in history, the ENIAC. To replace the punch card accounting computers of the day, the UNIVAC I was created as a commercial data processing system.

First generation computers

1946 through 1954 marked the existence of the first generation of computers. The first computer ever created, the ENIAC (Electronic Numerical Integrator and Calculator), was created at the University of Pennsylvania in 1947. The switching tubes in this computer were vacuum tubes. By the time EDSAC (Electronic Delay Storage Automatic Calculator) was launched in 1947, Von Neumann had already established the idea of stored programmes.

One of the five first-generation computers is the UNIVAC, which is also a first-generation machine.

UNIVAC 1108

In 1964, the 1108 was first launched. Thin-film memory, which was employed by the UNIVAC 1107 to store register data, was superseded by integrated circuits. Two key design enhancements, base registers and new hardware instructions, were included, in addition to faster components. As a programme was swapped in and out of main memory, its instructions and data could be stored wherever each time it was reloaded thanks to the two 18-bit base registers. The 1108 included memory protection, utilising two base and limit registers with 512-word resolution to facilitate multiprogramming.

Further details

Double precision arithmetic, double-word load, store, and comparison instructions were among the additional 1108 hardware instructions. Up to 16 input/output channels for peripherals are possible on the CPU. The 128-word ICR (Integrated Control Register) stack was the only component of the 1108 CPU that wasn’t developed using discrete component logic cards. These cards each had a 55-pin high-density connection that connected to a machine wire-wrapped backplane. Additional hand-applied twisted pair wiring was used in order to perform backplane connections with sensitive timing, connections between machine wire wrapped backplanes, and connections to the I/O channel connector panel in the lower area of the CPU cabinet.

Sperry Rand introduced the UNIVAC 1108 just as the first UNIVAC 1108 systems were being delivered in 1965. This model supported multiprocessing and had up to three CPUs; four memory banks totaling 262,144 words; and two independent programmable input/output controllers. The machine became the UNIVAC 1100/20 after Sperry Rand switched out the core memory for semiconductor memory. The last digit of this new naming scheme represented the number of CPUs in the system.

The next generation of computers

There are five generations of computers, with the UNIVAC being one of the earliest. According to the methodology used to evaluate the advancement of computer technology, the first generation was based on vacuum tube computers, the second on transistor computers, the third on integrated circuit computers, the fourth on microprocessor computers, and the fifth on ULSI technology incorporating artificial intelligence. The fifth generation is the most sophisticated and outpaces all earlier ones in speed.

CDC 1604 Computer

August 17, 2022 by admin Leave a Comment

Introduction

Seymour Cray and his team at Control Data Corporation created and created the 48-bit CDC 1604 computer (CDC). One of the first transistorised computers to be commercially successful was the 1604. In November 1959, the IBM 7090 was delivered (earlier). According to legend, Cray’s previous project, the ERA-UNIVAC 1103, was given the 1604 name by adding CDC’s initial street address (501 Park Avenue). Shortly after, a 24-bit version that had been reduced in size was created and given to NASA.

Table of Contents

In January 1960, the first 1604 was delivered to the U.S. Navy Post Graduate School for use in applications supporting significant Fleet Operations Control Centers, particularly for weather forecasting in Hawaii, London, and Norfolk, Virginia. Over 50 systems had been created by 1964. The CDC 3600, which replaced the 1604 and added five op codes, “was mostly compatible” with it.

Alike Machines

The Soviet nuclear weapons labs employed the 1604 design. Their BESM-6 computer, which went into production in 1968, was created with software compatibility with the CDC 1604 in mind [14], but it operated 10 times faster and had more registers.

Architecture

The CDC 1604’s magnetic core memory has a 32K by 48-bit word capacity and a 6.4 microsecond cycle time. It was divided into two banks of 16K words each, one bank containing odd addresses and the other bank containing even addresses. The average effective memory access time was 4.8 microseconds since the two banks were phased 3.2 microseconds apart. About 100,000 processes are carried out by the computer every second.

The CPU was equipped with a 15-bit programme counter (P), six 15-bit index registers, a 48-bit auxiliary arithmetic register (Q), and a 48-bit accumulator (A). [8]The Q register was typically used in tandem with A to create double-length registers AQ or QA, participate in operations involving multiplication, division, and logical products (masking), and temporarily store the contents of A while using A for another task.

Two 24-bit instructions were contained in each 48-bit word. The instruction format was 6-3-15: three bits for the “designator” (index register for memory access instructions, condition for jump (branch) instructions), six bits for the operation code, and fifteen bits for the memory location (or shift count, for shift instructions).

Uses

The United States’ first operational solid-rocket ICBM system was the Minuteman I. Two completely different ground station designs that were created separately exist today. The single silo design, which was more compact and attractive, had two redundant CDC 1604 computer systems, each with twin cabinets that held four 200 bps magnetic tape drives. Information for targeting control and guiding was pre-calculated using the computers. Prior to launch, results based on the current weather and targeting data were transferred into the missile. The Octave Chanute Aerospace Museum in Rantoul, Illinois, has model displays of both of these ICBM ground station concepts, including block replicas of the CDC 1604 computers.

CDC 924

The CDC 924 was a 24-bit computer that allowed “any input-output devices capable of interfacing with the 160 and/or 1604 computer”[17] to be used. Its six independent channels allowed for three simultaneous input operations while three channels simultaneously conducted output.

The 924’s advanced features, which contained 64 instructions, included six registers for indexes. Indirect addressing was reserved for the value “7”. An order to perform (in what the hardware reference manual called “a subroutine of a single instruction”). It consisted strong Storage Search guidelines.